This invention relates, in general, to III-V semiconductors, and more particularly, to a superlattice gate field effect transistor.
It is generally recognized that semiconductor-based multilayered superlattice and quantum-well structures offer the promise of high density integrated circuits. One such device is disclosed in U.S. Pat. No. 4,503,447 which issued to Iafrate et al. This U.S. patent also lists several prior patents which describe superlattice structures and methods for making the same. Accordingly, U.S. Pat. No. 4,503,477 is incorporated herein by reference. In addition to small size these structures offer new device possibilities having increased speed.
Accordingly, it is an object of the present invention to provide an improved superlattice gate heterostructure field effect transistor.
Another object of the present invention is to provide a superlattice gate field effect transistor having increased device speed and increased transconductance.
Yet a further object of the present invention is to provide a field effect transistor having gate electrodes aligned in the direction of current flow so electrons can achieve quasi 1-dimensional behavior providing significantly enhanced mobility and velocity.